The CDC 6600 had a very odd architecture. It had several I/O master processors, but the floating point engine was the slave.
This was prior to silicon microprocessors, so these processors were laid out on circuit boards with arrays of transistors as the active elements. Special care was taken in laying out the wire leads to ensure that signals arrived at the correct time as well as reducing line capacitance.
The wiki describes it as the evolutionary precursor of RISC (like ARM on your phone, for those less familiar).
This was prior to silicon microprocessors, so these processors were laid out on circuit boards with arrays of transistors as the active elements. Special care was taken in laying out the wire leads to ensure that signals arrived at the correct time as well as reducing line capacitance.
The wiki describes it as the evolutionary precursor of RISC (like ARM on your phone, for those less familiar).
The CDC 6600 ran at 10MHz.
https://en.m.wikipedia.org/wiki/CDC_6600
The Cray-1 would eventually run the "UNICOS" version of UNIX, and the FPU featured vector registers, which have been brought back in RISC-V.
The Cray-1 ran at 80MHz.
https://en.m.wikipedia.org/wiki/Cray-1