It's better than Verilog. It extends the types system, and makes user defined types easier to use. This helps with a lot with a big design with a lot modules acting as a layer of abstraction. The type system is stronger than verilog to some degree, but still is weakly typed to retain backward compatibility. VHDL still has much stronger type checking.
It also supports direct programming interfaces. For instance you have a chip your designing that needs to run software. Your test bench can call that C function to also test some software at the same time. You can also use it to speed up simulations by just modeling the input and output in C for a module. However, I prefer SystemC for this. It's great for behavior level simulation, and also runs quickly. It also is much easier to interface with any software you want to test with the design.
So I prefer SystemC for behavior models, and VHDL for gate level implementation. However, you can't really ignore verilog. Although, that depends where you are working and who you are working with. System Verilog is kinda of in between SystemC and VHDL.
It also supports direct programming interfaces. For instance you have a chip your designing that needs to run software. Your test bench can call that C function to also test some software at the same time. You can also use it to speed up simulations by just modeling the input and output in C for a module. However, I prefer SystemC for this. It's great for behavior level simulation, and also runs quickly. It also is much easier to interface with any software you want to test with the design.
So I prefer SystemC for behavior models, and VHDL for gate level implementation. However, you can't really ignore verilog. Although, that depends where you are working and who you are working with. System Verilog is kinda of in between SystemC and VHDL.
https://preview.ibb.co/hRz8qc/Screen_Shot_2018_02_07_at_9_21...