So cadence for instance lets you create device models. For instance if we are making a simple inverter some things you would need are:
width and height,
channel (width x height),
Zero bias voltage,
Zero-bias depletion capacitance (Planar and Sidewall),
Channel length,
Surface potential,
Oxide Thickness,
Carrier Saturation speed,
Junction Grading,
Area diffusion,
Transconductance,
Carrier Mobility,
The list goes on. So once you get this information you can create a model file that will let simulate your simple NOT gate. However, if you are starting from scratch such as there is something that does not exist in the standard cell library. You can't just measure these properties since the device does not exist yet. So you have run other simulation software to get reasonable values as calculating them by hand is not pretty. Also to get these values you may need information from the foundry. For instance Intel's finfet transistor behave differently in some regards compared to a traditional planar transistor (mainly the channel). Intel is not going to just tell you how they work so you can get accurate model of them without an NDA. Also a foundries process can effect your design as layer thickness can changes such capacitance. So the big thing is cadence does not let you model
Cadence also can only simulate a limited number of devices. So for large designs/system you can't simulate the whole thing. So you can only simulate sub components for big designs. It's also slow to simulate large design again pushing you to smaller simpler sub components. It's limited to things you can generate a net list for. It additionally will let calculate cross voltages. I could keep going on and on, but there is only so much I can cram into a hacker news response.
Depends on who you are working for and what you are making. However, you generally use 2 spins for a large device. I bet you have heard the term engineering silicon. That's usually the first spin. If there are problems usually the only changes are made to metal (wiring) layers of the masks. If a serious problem is discovered it may require a complete re-spin. That's if you mainly using the standard cell library provided by the foundry. If you are making something from scratch that's whole other story. However, you still generally build into your design other elements that let you shut off defective parts or include redundant elements to increase the chance of one elements working. So the designs also include a lot additional circuits and logic that you may not be aware of for debugging and testing purposes. If you can't get the device perfect you still may sell use it and publish an errata or more specify a more limited range of operation.
I'll just say I am computer engineer. My first job was at Micron.
Yes, God forbid you need native (low threshold) devices... want to minimize NWell spacing for stacked devices while preventing ESD latch-up... care about capacitance density or voltage variation.
Basically, if you are designing mixed-signal/analog then your PDK (Process Development Kit) either comes from a tier1 foundry (TSMC/UMC), the process is a very good copy (SMIC/GF), or you need a year of support and a one or more full time process support engineers.
The list goes on. So once you get this information you can create a model file that will let simulate your simple NOT gate. However, if you are starting from scratch such as there is something that does not exist in the standard cell library. You can't just measure these properties since the device does not exist yet. So you have run other simulation software to get reasonable values as calculating them by hand is not pretty. Also to get these values you may need information from the foundry. For instance Intel's finfet transistor behave differently in some regards compared to a traditional planar transistor (mainly the channel). Intel is not going to just tell you how they work so you can get accurate model of them without an NDA. Also a foundries process can effect your design as layer thickness can changes such capacitance. So the big thing is cadence does not let you model
Cadence also can only simulate a limited number of devices. So for large designs/system you can't simulate the whole thing. So you can only simulate sub components for big designs. It's also slow to simulate large design again pushing you to smaller simpler sub components. It's limited to things you can generate a net list for. It additionally will let calculate cross voltages. I could keep going on and on, but there is only so much I can cram into a hacker news response.
Depends on who you are working for and what you are making. However, you generally use 2 spins for a large device. I bet you have heard the term engineering silicon. That's usually the first spin. If there are problems usually the only changes are made to metal (wiring) layers of the masks. If a serious problem is discovered it may require a complete re-spin. That's if you mainly using the standard cell library provided by the foundry. If you are making something from scratch that's whole other story. However, you still generally build into your design other elements that let you shut off defective parts or include redundant elements to increase the chance of one elements working. So the designs also include a lot additional circuits and logic that you may not be aware of for debugging and testing purposes. If you can't get the device perfect you still may sell use it and publish an errata or more specify a more limited range of operation.
I'll just say I am computer engineer. My first job was at Micron.